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This section provides an overview of the key ACIS hardware components and clocking modes. This section is intended for information only, and does not describe all of the details of the various items.
Figure 1 illustrates the top-level interfaces to the DPA which affect the Science Instrument Software. The un-shadowed boxes are devices and the shadowed boxes contain processors which run portions of the ACIS Science Instrument Software.
FIGURE 1. DPA Interface Overview
The Back End Processor receives commands and sends telemetry to and from the Spacecraft via a Remote Command and Telemetry Unit (RCTU). The Back End Processor also controls the CCDs via the Detector Electronics Assembly (DEA), loads software into the Front End Processors, and acquires science data from the Front End Processors. The DEA drives the CCD clocks and biases, and passes the raw CCD pixel data back to the DPA's Front End Processors. The DPA Front End Processors reduce the raw pixel data into a series of candidate X-ray events, and transfer these events to the Back End Processor for further processing and inclusion in downlink telemetry.
This section provides a brief description of the CCDs and their arrangement. Refer to "Microcircuit, Charge-Coupled Device, (CCD) Monolithic, Silicon" (MIT-CSR 36-02308), and the "CCD-Description (CCID-10)" (MIT 36-02103) for detailed descriptions of the CCDs.
The CCDs are the X-ray detectors for ACIS. When placed in the focal plane, the CCDs detect X-rays focused by the High-Resolution Mirror Assembly. When out of the focal plane, the CCDs are illuminated by X-ray calibration sources.
ACIS contains a total of 10 CCDs. Each CCD consists of a 1024 x 1026 Imaging section, a 1024 x 1026 Framestore section and two serial output registers, each with two output nodes.
When viewed along the focal plane axis, the CCDs appear approximately as shown in Figure 3. The 10 CCDs are grouped into two arrays:
Six CCDs are used for each array, where the two most central Spectroscopy CCDs can be used for both Spectroscopy and Imaging.
FIGURE 2. Simplified CCD Arrangement
Each CCD consists of four main sections, as shown in Figure 3:
All rows and columns in the Imaging Section are clocked in parallel. The same applies to the Framestore. If rows are clocked in the Imaging Section, but not in the Framestore, the Image Rows are summed into row 0 of the Imaging Section. However, if the Framestore rows are clocked into the Serial Output Shift Registers without transferring the rows out of the output registers, the transferred Framestore rows are summed into the output registers. As rows are clocked in the Imaging Section, the effect is to clear the contents of the Imaging Section. Clocking the Framestore only clears the Framestore if no charge is transferred down from the Imaging Section.
Each Serial Output Shift Register is split into two halves. Each half has an associated output node. The hardware allows the output register halves to be clocked in following ways:
As the charge from the pixels is shifted along the registers, the effect is to clear the output registers.
FIGURE 3. Single CCD Pixel Flow Overview
An observer uses Timed-Exposure Clocking Operation to cause the CCDs to act like a photographic camera, exposing the CCDs for a period of time, and then capturing the acquired image.
When a CCD is being clocked in a Timed-Exposure fashion, the entire contents of the Imaging Section are transferred into the Framestore. Then, each row of the Framestore is clocked into the Serial Output Shift Registers and each pixel of the row is shifted out of the register halves to the corresponding output nodes. Meanwhile, the next image is being exposed in the Imaging Section. Figure 4 illustrates this process for a single exposure (see Figure 3, "Single CCD Pixel Flow Overview," on page 21 for a more detailed illustration of a single CCD).
FIGURE 4. Timed-Exposure Clocking Example
The analog pixel data is sent from the CCD's output nodes to the DEA CCD Controller board, which then amplifies, samples, and converts the pixel data to a digital form and transmits the digital pixel data to the DPA's Front End Processor. The Front End Processor then processes the data as an image.
To readout a portion of the CCD (subarray), one uses the same overall procedure, except several rows are transferred from the Framestore to the Serial Output Shift Register before starting to read the output register. This effectively "skips" the first collection of rows and saves the time used to transfer these rows out of the output register.
An observer uses Continuous Clocking to obtain fine timing event information from a certain area of a CCD.
When a CCD is being clocked in a continuous fashion, the CCD Imaging Section is shifted down one row into the Framestore, and the Framestore is shifted down one row into the Serial Output Shift Registers. The output registers are then clocked out. This repeats continuously for the duration of the mode. This clocking mode provides a detailed time series of events in each column of the CCDs. The time-resolution of this mode is best for a point-source, and depends on the distribution of X-rays across the rows of the Imaging Section, and on the time it takes to clock the CCD. Figure 5 illustrates this process.
FIGURE 5. Continuous Clocking Example
Summing across rows is accomplished by shifting a number of Framestore rows into the Serial Output Shift Register before clocking out the output registers. This sums the rows as they are clocked into the output register.
Summing across columns is achieved by controlling the integration of the pixel signals at the output nodes as they are being clocked out of the Serial Output Shift Registers.
This section provides a brief description of the Detector Electronics Assembly (DEA). Refer to the "DPA/DEA Interface Control Document" (MIT 36-02205) for a more detailed description of the interface to the DEA. The Detector Electronics Assembly (DEA) is responsible for clocking the CCDs and for converting the analog CCD pixel data to a digital representation and sending the converted data to the Digital Processor Assembly for event detection and processing.
Figure 7, "DEA Interface Overview," on page 25 illustrates the main components within the Detector Electronics Assembly (DEA) and how each component maps to their respective CCDs. The DEA consists of eleven boards: 10 CCD controller boards, one for each CCD in the system, and one interface board, which contains the focal-plane temperature controller. Each CCD controller board consists of the following software-commandable subsections, shown in Figure 6:
FIGURE 6. DEA CCD Controller Block Diagram
FIGURE 7. DEA Interface Overview
Each DEA board contains command decoding logic, which is responsible for listening for commands from the interface, and, when enabled, for forwarding the received commands on to the appropriate board subsection to be executed. In general, the procedure for commanding the DEA involves first sending a command to enable and disable the various listeners on the DEA boards, and then sending one or more commands to the activated boards. When the command decoder on each board is enabled, it forwards any subsequent commands onto the addressed subsections. When the decoder is disabled, it ignores any subsequent commands until it is re-enabled.
Figure 8 illustrates the major programmable components of the sequencer logic.
FIGURE 8. DEA Sequencer Components
The DEA sequencer consists of two main programmable sections, the Program RAM (PRAM), and the Sequencer RAM (SRAM). The Program RAM contains what can be considered the object code for a given CCD clocking sequence. The Sequencer RAM contains the equivalent of microcode. In flight, we expect to re-program the PRAM for each set of CCD clocking options. Although we plan to re-load the SRAM for each science run, we expect to hardly ever have to change the content of the loaded SRAM image.
Program RAM (PRAM) contains a series of 16-bit command word pairs. Once running, the sequencer logic executes each of these PRAM pair in series. There are two types of PRAM command pairs:
The instrument software can load the contents of PRAM by command, and may command the PRAM to provide the contents of any given location as a status response.
Sequencer RAM (SRAM) contains blocks of 64 16-bit sequencer words. Each bit of a sequencer word corresponds to one of the CCD clocks, Video control signals, or Pre-amplifier control signals. The state of the bit, 0 or 1, indicates whether its corresponding signal should be asserted or de-asserted when the sequencer word is invoked.
When a PRAM couplet command is executed, the PRAM couplet selects which SRAM block to execute and how many times to execute the block. Upon each sequencer clock cycle, the sequencer then sequentially fetches and invokes each SRAM word from the addressed block. The effect is to produce a series of timed state changes on the output clock signals.
The instrument software can load the contents of SRAM by command, and may command the SRAM to provide the contents of any given location as a status response.
The Digital-to-Analog Converter (DAC) Banks provide conditioned levels for the actual clock and bias signals output by a given DEA board. Each level provided by the DAC is commandable by the instrument software.
Various subsections on a given DEA board provide housekeeping values. The instrument software can obtain a given value by commanding a board's Housekeeping Multiplexer to convert and send a given analog signal in the form of a status response.
The DPA communicates with the outside world via a Remote Command and Telemetry Unit (RCTU). The RCTU connects the DPA's Back End Processor to the spacecraft's Command and Telemetry Unit, which in-turn, communicates with the ground and the spacecraft's On-Board Computer (OBC). The software executing in the Back End Processor receives commands via one of the RCTU's Serial Command Ports, and sends Science Data Telemetry via one of the RCTU's Serial Telemetry Ports. The science telemetry data appears in the "Science Data" portion of the ACIS telemetry stream. The Back End Processor can also control certain bits in the RCTU's discrete telemetry, which appear in the "Engineering" portion of the ACIS telemetry stream.
This section provides a brief description of the Digital Processor Assembly's Back End Processor. For a more detailed description, refer to the "DPA Hardware Specification and System Description" (MIT 36-02104). Figure 9 illustrates the major components within the ACIS Back End Processor. Although there are physically two Back End Processors on ACIS, only one of them is active at any time. The ground switches between the two using a discrete command to the hardware. The ACIS software has no built-in knowledge of this redundancy.
FIGURE 9. Back End Processor Overview
The Mongoose Microcontroller consists of a core R3000 processor, a reduced R3000 System Co-processor, and a set of internal devices to assist hardware designers. The System Co-processor is functionally equivalent to a standard R3000, except it does not support address translation (via the Translation Look-aside Buffer), nor does it support a processor version register. Figure 10 illustrates the additional components within, or associated with, the Mongoose.
FIGURE 10. Mongoose Component Overview
The Mongoose Microcontroller consists of a core MIPS R3000 processor and an on-board DMA controller, external interrupt interface, UART, Watchdog Timer and General Purpose Timer. The chip also has built-in external memory and device interface logic. Rather than providing a Translation-Look-Aside-Buffer (TLB), the Mongoose virtual addresses have fixed relationships to physical memory and memory-mapped devices. The Mongoose does not use tagged-cache, but rather maps the R3000 cache addresses to fixed fast instruction and data RAM locations.The instruction RAM and data RAM are distinct in that the instruction RAM (I-cache) is readable and writable as data only via an interface port, and instructions cannot be executed from data RAM (D-cache). External memory, however, can be read from and written to as data, and can also contain executable code.
This section provides a brief description of the Digital Processor Assembly's Front End Processors. For a more detailed description, refer to the "DPA Hardware Specification and System Description" (MIT 36-02104). Figure 11 illustrates the major interfaces to the DPA's Front End Processors. Refer to Figure 10, "Mongoose Component Overview," on page 30 for the components surrounding the Mongoose Microcontroller.
FIGURE 11. Front End Processor Overview
The Front End Processor is responsible for processing raw digital CCD pixel data from the Detector Electronics Assembly and producing events. It transfers the extracted event information to the Back End Processor for further selection and processing.
The Boot RAM, Scratch RAM (not shown), Pixel Bias Buffer, Pixel Buffer and Overclock Buffers are all memory-mapped into the Back End Processor's address space using a shared-memory interface (not shown).
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