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The Digital Processor Assembly (DPA) is a computer-based on-board data system which receives digitized data from the DEA and commands from the RCTU, processes data according to the commanded mode, and submits the processed data to the RCTU for eventual telemetry to the ground. The DPA is customized to meet the unique requirements of the CCD data acquisition and reduction tasks, and to achieve satisfactory compression of the incident data stream to meet the limitations of the telemetry capacity.

The DPA must be capable of receiving 28 Mbits/sec of raw pixel data, corresponding to an exposure rate of 3.3 sec for six simultaneously active CCDs, and, after post-processing by the DPA, reducing the data rate to conform with the maximum allocated telemetry bandwidth of 24 kbits/sec.

The DPA is composed of two varieties of processor boards.

Backend Processor - which oversees supervisory tasks including uplink, downlink and CCD control, and also performs the X-ray event packetizing.
Frontend Processor - which processes CCD data on a pixel-by-pixel basis, detects candidate X-ray events and passes them on to the BEP.

There are two BEPs in the DPA, each of which is cross-strapped to the other, but only one of which is running at any time (while the other stays in hot standby mode). The BEP tasks are relatively large timescale (i.e. on the order of seconds) and the event processing burden is comparatively low (due to the reduction in raw rate accomplished by the FEP processors). The BEP processors are redundant, and should one fail the other will be able to assume control. A non-volatile copy of the flight software resides on each BEP processor, a portion of which is downloaded to the FEP processors as they are booted.

There are six FEPs in the DPA, each listening to a selected DEA board. Control of which DEA board is active is handled by the DPA as the result of commands from the ground link. Should an FEP processor fail, then ACIS can only process data from five CCDs, but the CCDs can be any of the ten CCDs in the total flight array. Hence overall ACIS performance can be compensated by reassigning FEPs using software commands.

Figure 2.23:   DPA Functional Block Diagram
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The overall functional interrelationships between the various components of the DPA, the CCDs, and RCTUs is shown in Fig. 2.23.

next up previous contents
Next: DPA Electronics Design Up: 2.3.7 DPA Hardware Previous: 2.3.7 DPA Hardware

John Nousek