Next: 188.8.131.52 Output Amplifiers Up: 2.3.1 CCD Chips Previous: 184.108.40.206 Description of Physical
Each charge packet is shifted through the CCD by repeated cycles of clock signals applied to the electrodes of the CCD. Each pixel is covered by 3 electrodes, and the corresponding electrodes over each pixel are connected in parallel. A single row (column) shift is executed by a cycle of the 3 clock phases in the parallel (serial) registers. Operating mode changes which change the frame time or image format are simply obtained by a re-arrangement of the sequence of clock cycles.
There are only 4 basic operations:
After collection, data may be shifted to the store section by simultaneously clocking the image and store sections in parallel (1024 row shifts to clear the whole image into the store section).
The normal mode of readout is then to apply a store shift cycle to place one row into the serial registers, then the serial register is read out by column shifts of this register, interspersed with pixel read cycles. To read out the four amplifier nodes requires each split serial register to be fed with 256 cycles of shift and pixel reads.
The time required to readout a CCD frame, which establishes the intrinsic timing resolution of the detector, is dominated by the pixel read cycle. This requires the amplifier node to be reset to a reference voltage; then the signal charge is clocked onto this node, and the resulting voltage change off-chip must be sampled. To minimize the noise bandwidth, the sampling process must be of order 10 s long, whereas the shift process can be much faster.
To increase the speed of image readout, unneeded pixels should not be sampled. (This might occur if the scientific motivation were to study only a single point source in the center of the image, for example.) These unneeded pixels may be ignored by repeatedly shifting the serial register without performing a pixel read cycle. Rows may be ignored by repeatedly shifting the store register without performing the row readout. Thus a combination of the correct store cycles, serial cycles and pixel read cycles can be constructed in order to read out only a fraction of the whole CCD frame.
It is expected that the basic individual clock waveforms for each cycle will be adjusted on the ground for optimum voltage swings and overlaps, and would infrequently need to be changed. The user would only have control over the observation mode image format. (See section on observation modes). The actual generation of these programmable sequences to be uploaded to the ACIS instrument is performed by the ASC.